This tutorial will cover the hardware and software setup for the MAX II EPM240 CPLD. We will also make a simple logic design in Quartus to upload to the CPLD.
This little dev board can be picked up on eBay or Aliexpress for around 10 bucks(including the USB blaster). It’s cheap, easy and simple compared to some of the other FPGA dev boards. Despite that, I didn’t find a lot of tutorials and projects(compared to the Arduino stuff) with this board so I thought I’d make a tutorial.
First, you will have to download and install Quartus 13.1 (there are other versions that support the MAX II CPLD but I will be using 13.1).
You can find Quartus 13.1 web edition here on Intels website but you will have to make an account and register as a company to be able to download the software(apparently you can just make up a company as they don’t really check).
Alternatively, you can go on pirate bay, search for Quartus 13.1 web edition and download it from there.
After having downloaded Quartus go ahead and install it. I am not going to cover the installation here as it’s just like installing any other program. Check all the boxes, agree to everything, click next without reading, … you know the drill ;).
Connect the USB blaster to your computer. I believe that any drivers should get installed automatically so you don’t have to worry about that. If they don’t you can perform a manual install:
Connect the programmer, open device manager, find your device, open the properties and select the driver tab, click update driver, “Browse my computer for drivers” and select the “path to Quartus installation”\quartus\drivers\
Next, connect the ribbon JTAG cable from the USB blaster to the development board.
Making a project
Making a design
We are going to make the “Hello World!” of digital electronics. A really basic logic design that will blink an LED.
We will take the onboard clock(2 MHz) and lower it’s frequency down to something the human eye can actually perceive as blinking. We will achieve this using a counter that will act as a frequency divider. The counter will be implemented in Verilog HDL. Then we will output the signal to the onboard LED.
module counter(clk, out); input clk; output out; reg out; reg[23:0] count; always @(posedge clk) begin count <= count + 1'b1; out <= count; end endmodule
Click on the location cell of the CLK input and write PIN_12 this pin has a clock signal connected to it on the development board. For the OUT output write PIN_77 which is the pin that connects to the onboard LED.
Note: If the inputs aren’t visible under Node Name column compile the project(by pressing the play button in the toolbar).
The pins are now assigned and you can also see them graphically represented on the picture above. The pin planner can now be closed.
Note: The pin numbering in the pin planner directly corresponds to the pin numbering on the development board.
The output frequency can be altered by changing this line of Verilog code:
from: out <= count;
to: out <= count;
The lower number you put in the fewer times the input signal will get divided. As a result, the output frequency will be higher. You can see that in the second part of the video. The LED looks as if it’s always on because the frequency is too high. But you can see the waveform captured with a logic analyzer on the screen.